Testing and debugging integrated circuits and other complex digital electronics is a persistent problem. There are two parts to the problem: first, gaining access to the signals in the circuit in order to stimulate the circuit in many different ways and measure its response, and second, devising a set of test stimulations that thoroughly exercises the circuit. This invention addresses the first problem: it discloses a novel scheme for providing access to signals on intergrated-circuit chips, boards, or any other collection of digital electronics.
Large digital systems are constructed by joining together smaller systems using interfaces. Most often, an interface is evident in the physical construction of the system. For example, an integrated circuit chip has as its interface its pins 16, 18, 24, 48, or more connections by which the integrated circuit is connected into a larger assembly. Similarly, a printed-circuit board has as its interface an edge connector to plug into a backplane; it may also have additional connectors mounted elsewhere on the board to accept connection cables. Many interfaces are not so obvious however. Within an integrated-circuit chip, there are often interfaces. For example, a microprocessor will have distinct sections for the Arithmetic Logic Unit (ALU), a sequencer, and a memory interface among many others. A distinct interface exists between the ALU and the sequencer, consisting of control signals that the sequencer will use to govern the operation of the ALU and signals generated as the result of ALU operators that will govern the subsequent operation of the sequencer. In general, a signal at the interface may be bidirectional.
A convenient way to debug and test a digital subsystem is to stimulate and observe signals at the subsystem's interface. Thus, for example, a chip is plugged into a "chip tester" or a printed-circuit board into a "board tester" to carry out the tests. Each signal at the interface is connected to a testing device so that it may be stimulated or observed. A significant disadvantage of testers built this way is the considerable number of connectors and signal stimulation and measurement electronics required.